Technical articles A selection of technical papers and articles, relevant to your industry.
Semiconductor industry  | Beyond 3G & Emerging Technologies
Tord Wingren MD, Samsung Electronics (September 2005)
Contents: IT Trends 4G Terminal Requirements Mobile Comm. Roadmap -3GPP/IEEE Evolutions Wireless Broadband
Source: Presentation from Moore and More Chips? Seminar | | | The Return of Innovation
David May, Set Squared (September 2005)
Contents: Long term trends Moore’s Law Increasing performance Decreasing cost General purpose computing The Exabyte effect Computing without power Wearables Software Software and Algorithms Generic products The Fabless, IP-less chip company Innovations in Architecture Concurrency Processor arrays Innovations in Design Robotics New technologies Summary
Source: Presentation from Moore and More Chips? Seminar | | | Moore & More Chips? Breaking the Law
Jeremy Milne, Quester (November 2005)
Presentation from seminar on 'MOORE & MORE CHIPS? What are the market opportunities for the next generation of IC start-ups?'
Source: Presenation from seminar on 'MOORE & MORE CHIPS? What are the market opportunities for the next generation of IC start-ups?' | | | Desktops out, handhelds in (low power chips)
S Josifovska (October 2004)
This article outlines the current trend away from desktop computers to portable devices such as mobile phones, MP3 players and notebook computers. It then presents a review of how some chip manufacturers are developing low-power high-speed devices specifically for these markets. The main emphasis is on how power consumption is being held as low as possible for battery-powered equipment.
Source: Power Engineer - October 2004 | | | Absolutely Fabless
Luke Collins (October 2004)
Executives gathered at the IEE's recent Fabless Forum to find out how the industry will evolve. Foundries will soon encroach on the chip companies who have their own fabs, they discovered.
Source: Electronics Systems and Software - October 2004 | | | Two Heads Are Better Than One
Douglas Hamilton, Freescale Semiconductor (October 2004)
Superscalar processors have become increasingly power hungry. Dual-processor designs can offer one way of increasing performance without pushing power consumption beyond what can be used in many embedded applications.
Source: Electronics Systems and Software - October 2004 | | | Low-Power Strategies
Ed Huijbregts, Lars Kruse and Eric Seelen, Magma Design Automation (October 2004)
Chip designers can now deploy a number of techniques to minimise power in their designs, attacking both dynamic power consumption and the rising threat of static power consumption caused by current leakage.
Source: Electronics Systems and Software - October 2004 | | | Foundries make power moves (software development)
Nick Flaherty (August 2004)
As foundries move over to the 90nm and 65nm generations, they are having to make deals with tools suppliers and sometimes each other to ensure the designs make it to production.
Source: Electronics Systems and Software, August 2004 |  | On a higher level
N Flaherty (July 2004)
Electronic design automation (EDA) companies are trying to push their tools up to the 'electronic system level'.
Source: | | | Power in motion
R Pool (June 2004)
Interview with Alex Lidow, chief executive of US-based power electronics firm International Rectifier.
Source: Power Engineer, June 2004 | | | Clear future direction (Member Voices)
R Woods, The Queen's University, Belfast (June 2004)
Realising the full capabilities offered by silicon technology requires a multi-disciplinary approach to creating and developing new products and applications.
Source: IEE Review, June 2004 | | | Model for competitiveness
J Walko (June 2004)
The EU needs to change its tax system to help its electronics industry to compete in global markets, according to Pasquale Pistorio, president and CEO of STMicrolectronics.
Source: IEE Review, June 2004 | | | Boosting competitiveness
M Pereira (April 2004)
Asset reuse, cost-cutting, outsourcing to Asia and consolidation in the EMS business are expanding the list of challenges for Agilent Technologies.
Source: IEE Review, May 2004 | | | Taking the lead
M Deaves (March 2004)
This article looks at how electrical manufacturers are responding to the EU Directive on Restriction of Hazardous Substances (RoHS), which from 2006 will ban the sale of equipment containing or manufacured using cadmium, mercury, hexavalent chromium, and lead, as well as certain flame retardants.
Source: Manufacturing Engineer, April 2004 | | | Cut-price tricks for custom chip masks
C Edwards (February 2004)
Mask costs seem to be putting ASICs out of reach of many users, but there are ways to make big savings on masks - as long as the other trade-offs work for you.
Source: Electronics Systems and Software, February 2004 | | | Spotlight - Silicon Valley North
S Josifovska (April 2003)
Report on the clustering of high technology businesses in and around Ottawa, Canada.
Source: IEE Review May 2003 | | | The new micro giant
L Collins (April 2003)
Reports on the rapid development of the Chinese semiconductor industry.
Source: IEE Review May 2003 | | | Centrino puts chip industry in a hot spot
L Collins (March 2003)
Intel's Centrino campaign could corner the Wi-Fi market that other chip makers are hoping will pull the industry out of the current downturn. Centrino combines a mobile processor, chipset and Wi-Fi interface validated to work together. Manufacturers will only be able to use the Centrino brand if they buy all three.
Source: IEE Review April 2003 | | | Poised to pounce
R Dettmer (March 2003)
Interview with John East, president and CEO of Actel, about prospects for the semiconductor industry.
Source: IEE Review April 2003 | | | Chips for Everything: Britain?s opportunities in a key global market
House of Lords Science and Technology Committee (December 2002)
Urgent action by Government and business is needed to prevent substantial scientific and commercial opportunities in the international computing market being squandered. This call is made in this report from the House of Lords Science and Technology Committee.
Source: House of Lords |
Software development and tools | | Calibration of Active Phased Array Antennas
Radar, Sonar & Navigation Professional Network (March 2005)
This event took place on Tuesday, 8 March 2005 at The IEE, Savoy Place and was organised by the IEE Radar, Sonar and Navigation Professional Network. This event addressed aspects of ongoing research in the area of active phased array antennas due to them becoming affordable for wide range of radar and communication applications,
Source: Active Phased Array Event | | | Software patents: Are they a help or a hindrance to innovation?
J Walaski, Venner, Shipley & Co. (October 2004)
This article delves into the debate on software patents and attempts to explain the true position, and the reason why this debate and its possible outcomes are important to the future of the UK electronics industry.
Source: Engineering Management - October 2004 | | | Microwaves meet digital signal integrity (digital design)
Randy Weber, Agilent Technologies (August 2004)
Digital design now demands mixed-signal design techniques to ensure that high-speed onboard signal traces will work in the target system. The speeds now demanded by protocols such as PCI Express even demand the use of mixed-signal techniques from the microwaves world.
Source: Electronics Systems and Software | | | Embedded earthquakes
D Lenton (July 2004)
Linux is helping Wind River to negotiate a tectonic shift in the embedded software market.
Source: IEE Review, July 2004 | | | Dying hardware changes attitudes in defence
(June 2004)
Even as it entered service in 1997, the US fighter aircraft the F22 Raptor was beginning to look out of date. Not to the F15 Eagle pilots who were angling to fly replacement for their aircraft which now has serious problems with obtaining spare parts; it represented the latest in stealth and other technologies. But the F22 was based on components that their manufacturers thought should be phased out in favour of newer models and suffered during its development from components being marked as close to the end of their production lives before the aircraft itself was to be delivered to the US Air Force.
Source: Information Professional, June 2004 | | | Evaluating a systemC-based design flow
T Schubert et al (June 2004)
It takes a number of languages and re-implementation steps to turn an architechture into a design. A refinement-based SystemC flow could reduce the effort with no loss in silicon efficiency. One team decided to find out whether that was the case.
Source: Electronics Systems and Software, June 2004 | | | Schemas are the answer (Industry View)
R Howarth, Beach Solutions (April 2004)
Change management is practically synonymous with Electronic Design Automation (EDA). After all, EDA tools are at the heart of an extremely challenging industry. But to remain relevant, the EDA industry needs to develop and evolve the tools it offers. New trends and issues that affect silicon design have to be quickly addressed and solved.
Source: IEE Review, May 2004 | | | Putting conditional access into set-top boxes
M Hutchison (February 2004)
Software can represent one of the biggest costs of system design. Prepackaged support software for systems such as set-top box decoders can reduce the development burden with a variety of techniques.
Source: Electronics Systems and Software, February 2004 |
System and hardware description languages | | Modelling of real-time constraints using SDL for embedded systems design
A Alkhodre, J-P Babau and J-J Schwarz, Laboratory of L3i, INSA-Lyon (July 2002)
The use of SDL has arisen as a promising way of dealing with the increasing complexity of embedded real-time systems. However, SDL does not take into account non-functional aspects, which are especially important in the context of real-time systems. A real-time semantic extension to SDL for real-time systems modelling is proposed.
Source: Computing and Control Engineering Journal, August 2002 |
System design and architecture | | One-Week Prototyping of Embedded Systems
Professor Daniel Gajski, University of California, Irvine, USA (October 2005)
Presentation from the IEE FPGA Developers Forum 2005
Source: Presentation from IEE FPGA Developers Forum 2005 | | | FPGA - the most credible path to higher-performance embedded computing
Tim Allen, Senior Director, Embedded Systems Engineering, Altera, USA. (October 2005)
Covers the following: - Embedded Development Challenges
- C-to-Hardware − Technology Initiative − Accelerator Overview
- Design Considerations
- Examples & Results
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Protecting Intellectual Property in FPGA Devices
Yankin Tanurhan, Director of IP, Actel, USA (October 2005)
Covers the following: - Processors in FPGAs
- The need for security
- Differing levels of protection
- Methods of IP theft
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Applications and development methodology for FPGA clusters
Martin Olsson, Chief Technology Officer, Synective Labs, Sweden (October 2005)
Covers the following: - Synective Labs Introduction
- Large FPGA Systems – Architecture and Applications
- Case study – Semiconductor Lithography
- Managing FPGA Design Like Software
- Architecture Layering and Design Methodology
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Multi-FPGA systems for High Performance Computing Applications
Malachy Devlin, Chief Technology Officer, Nallatech, UK (October 2005)
Covers the following: - History of FPGAs
- Commercial Realities of FPGA Computing
- Creating Multi-FPGA systems
- FPGA based HPC application examples
- Should Von-Neumann Architectures retire
- Future possibilities for FPGA Computing -Homogeneous -Heterogeneous -Polymorphic Computing
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Tools for System Level Design
Mark Dickinson, Vice-President, European Technology Centre, Altera UK (October 2005)
Covers the following: - FPGA’sUnique Value Proposition
- The Cost OptimisationProblem
- Real World System-Level Tool Examples −Wireless Modem IF Processing −Automotive Infotainment System
Source: Presentation from IEE FPGA Developers Forum 2005 | | | FPGA SoC for Medical Imaging
Colin Hall, Principal Engineer, Optos PLC, UK (October 2005)
Presentation from IEE FPGA Developers Forum
Source: Presentation from IEE FPGA Developers Forum 2005 | | | FPGA-Based Speech Enhancement
David Halupka, University of Toronto, Canada (October 2005)
Outline: - Need for speech enhancement
- Multi-sensor speech processing
- Pros of our method vs. competing methods
- Why hardware? Why FPGA?
- System overview and details
- Performance summary & conclusion
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Complex DSP System Design using FPGAs
Dr John McAllister (October 2005)
Contents: FPGA DSP system design –Varied demanding real time requirements –Anomoliesin current design approaches –Design process compromise for FPGA-centric systems Abhainn –Virtual Platform Configuration (VPC) Design •Model Based Design •Rapid Implementation •Transformation for embedded optimisation –Gedae •Geometric Dataflow Modelling •Optimisation Techniques –Core Design Requirements •Flexibility for transformation Future Application Span
Source: Presentation from IEE FPGA Developers Forum 2005 | | | FPGAs in switched serial backplane architectures
Paul Burns, Quixilica FPGA Products Team Manager, QinetiQ UK (October 2005)
Overview: Sensor processing applications High-end sensors generate massive amounts of data – E.g. 10-bit ADC @ >2GHz – Data rate exceeding 20Gbps per channel Even modest sensors in multi-sensor systems generate large amounts of data – E.g. 16-bit ADC @ 125MHz – Data rate of 10Gbps for 5 channels Processing can increase data rate through up-sampling – 1Gbps sensor data rate can become >20Gbps between algorithm stages
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Developments in Physical Synthesis to solve timing closure in 90nm FPGAs
Gael Paul, Synplicity USA (October 2005)
This presentation covers: The Timing Closure Problem -Traditional delay models break down Simultaneous Synthesis and Placement -Is it enough for FPGAs? Graph-Based Physical Synthesis -When wires matters most Optional Design Planning for Advanced Users -Design Analysis -Timing Islands
Source: Presentation from IEE FPGA Developers Forum 2005 | | | Calibration of Active Phased Array Antennas
Radar, Sonar & Navigation Professional Network (March 2005)
This event took place on Tuesday, 8 March 2005 at The IEE, Savoy Place and was organised by the IEE Radar, Sonar and Navigation Professional Network. This event addressed aspects of ongoing research in the area of active phased array antennas due to them becoming affordable for wide range of radar and communication applications,
Source: Active Phased Array Event | | | Shake it up [Power supply design]
R Hill, C&D Technologies (December 2004)
Power supply design for next generation distributed power architectures isn't easy. To boost functionality and increase power densities, design engineers are having to deliver fresh combinations of technologies, topologies and materials.
Source: Power Engineer - December 2004 | | | Seconds out [Distributed power architectures]
S Josifovska (December 2004)
It might have been the cottage industry of yesteryear, but the semiconductor power sector commands profits and innovations that tell a different story today. The industry has undergone many changes, and some of the most interesting relate to the evolution of power architectures.
Source: Power Engineer - December 2004 | | | Visionary Placement
Paul Rooimans, MYDATA (October 2004)
The growing trend for miniaturisation has challenged the abilities of electronics manufacturers to accurately place sensitive, high-performance components without damage. Somewhat surprisingly it is conventional vision systems technology that has emerged as the answer to these anxieties.
Source: Manufacturing Engineer - October 2004 | | | Sleight Of Hand
Nial Murphy (October 2004)
Security is often overlooked in embedded systems. But it is emerging as an area where urgent action needs to be taken, to protect not just business models but customers.
Source: Electronics Systems and Software - October 2004 | | | Exploiting PFGA I/O For Cheaper PCBS
Dave Brady and Rick Stroot, Mentor Graphics (October 2004)
It's not widely known but FPGAs have the flexibility to reduce PCB re-spins and manufacturing costs. Designers can address PCB manufacturing complexities by exploiting new features of modern FPGA architectures to reduce PCB routing congestion and the number of design iterations.
Source: Electronics Systems and Software - October 2004 | | | Cut Memory Accesses For Lower-Power Displays
Lieven Hollevoet, Andy Dewilde, Kristof Denolf, Francky Catthoor and Filip Louagie, IMEC (October 2004)
Memory accesses consume a lot of power when putting images on screen in a portable terminal. A two-step optimisation method can dramatically cut power consumption with further gains being achievable with next-generation display technologies.
Source: Electronics Systems and Software - October 2004 | | | Two Heads Are Better Than One
Douglas Hamilton, Freescale Semiconductor (October 2004)
Superscalar processors have become increasingly power hungry. Dual-processor designs can offer one way of increasing performance without pushing power consumption beyond what can be used in many embedded applications.
Source: Electronics Systems and Software - October 2004 | | | Low-Power Strategies
Ed Huijbregts, Lars Kruse and Eric Seelen, Magma Design Automation (October 2004)
Chip designers can now deploy a number of techniques to minimise power in their designs, attacking both dynamic power consumption and the rising threat of static power consumption caused by current leakage.
Source: Electronics Systems and Software - October 2004 | | | Microwaves meet digital signal integrity (digital design)
Randy Weber, Agilent Technologies (August 2004)
Digital design now demands mixed-signal design techniques to ensure that high-speed onboard signal traces will work in the target system. The speeds now demanded by protocols such as PCI Express even demand the use of mixed-signal techniques from the microwaves world.
Source: Electronics Systems and Software | | | Analogue switch design in video systems
Jeff Ju, Fairchild Semiconductor (August 2004)
Optimally interfacing video switches within consumer video designs is increasingly a challenge. This article looks at two design cases for DVD R/W and LCD TV applications in order to fully understand how to improve the signal data path to optimise video switch performance.
Source: Electronics Systems and Software, August 2004 | | | Microwaves meet digital signal integrity (digital design)
Randy Weber, Agilent Technologies (August 2004)
Digital design now demands mixed-signal design techniques to ensure that high-speed onboard signal traces will work in the target system. The speeds now demanded by protocols such as PCI Express even demand the use of mixed-signal techniques from the microwaves world.
Source: Electronics Systems and Software, August 2004 | | | Live fast, die young
C Evans-Pughe (July 2004)
Shrinking feature sizes and GHz clock rates are undermining the life expectancy of mainstream semiconductor devices.
Source: IEE Review, July 2004 | | | On a higher level
N Flaherty (July 2004)
Electronic design automation (EDA) companies are trying to push their tools up to the 'electronic system level'.
Source: IEE Review, July 2004 | | | Rematch for CISC
C Edwards (June 2004)
The Complex Instruction Set Computer (CISC) seemed consigned to the dustbin of history. But it's coming back to deal with a growing need for custom instructions to get more performance out of processors beyond multimedia applications.
Source: Information Professional, June 2004 | | | Think outside the bus
C Rowen, Tensilica (June 2004)
The system-on-chip environment provides many alternatives to bus-based communications when data needs to be transferred at high-speed or deterministically between processors.
Source: Electronics Systems and Software, June 2004 | | | Bus succession
P Marsh (June 2004)
With both chip-to-chip and backplane interconnects, designers face a dilemma when choosing a next generation technology.
Source: Electronics Systems and Software, June 2004 | | | FPGA I/O: when to go serial
B J LaMeres, Agilent Technologies (June 2004)
Field-programmable gate arrays now incorporate high-speed serial interfaces. But which are the right types of interface and clocking scheme to use?
Source: Electronics Systems and Software, June 2004 | | | Power mad
J Frenkil, Sequence Design (June 2004)
What is commonly referred to as "low-power design" actually comprises two different, but related, activities: power minimisation and power-integrity management.
Source: Power Engineering, June 2004 | | | Scaling is dead, long live innovation!
J Walko (June 2004)
Moving to 90nm process geometries will mean major changes in design and manufacturing approaches for semiconductor firms.
Source: IEE Review, June 2004 | | | Voltage limit: processor lives depend on it
R Berthiaume, Fairchild Semiconductor (March 2004)
The delicate nature of transistors in modern processors mean that exceeding the rated voltage can take years off their lifetime. But there are regulation techniques that allow for better performance without requiring the use of many additional components.
Source: Electronics Systems and Software, April 2004 | | | Networks go to chip level
L Collins (March 2004)
Wire delays on chip mean designers will have to embrace ways of connecting cores together that dispense with traditional buses.
Source: Electronics Systems and Software, April 2004 | | | The connection conundrum
P Marsh (March 2004)
The choice of package for a key chip can have dramatic effects on the yield, and cost, of a PCB. A fine-pitched single chip could work out more expensive overall.
Source: Electronics Systems and Software, April 2004 | | | Keep it simple
R Rossetti, Fairchild Semiconductor International (March 2004)
As consumers demand more functionality in wireless handsets, power management integration is becoming critical. Fortunately, even high levels of integration do not require specialised processes. The author considers the trade-offs that must be considered in defining a microcontroller-based power management architecture.
Source: Power Engineer, April 2004 | | | Focus on mask yield for lower cost designs
K Rygler, Rygler & Associates (March 2004)
As mask costs spiral out of control, attention is shifting to the root causes of the problem and how decisions at the outset could help keep custom-chip projects viable.
Source: Electronics Systems and Software, April 2004 | | | Bug to basics
C Edwards (March 2004)
In an attempt to contain rising design costs, chipmakers have resorted to reusing circuits and architectural blocks from previous designs, and new companies have emerged to supply these IP (intellectual property) cores. However, continued growth in this sector depends on the industry solving its quality problems.
Source: IEE Review, March 2004 | | | Count three for wearable computers
S Woolley et al (February 2004)
The number three dominates the world of ubiquitous computing and this is set to continue with the evolution of wearable computing where three different types of device should satisfy the wide variety of uses for computers people can attach to themselves.
Source: Electronics Systems and Software, February 2004 | | | Variability puts timing margins under pressure
G Curren (February 2004)
On-chip variation has come from nowhere to become one of the single biggest issues facing designers of ICs at 130nm and below. There are no tools that deal with it, but there are techniques that can be used to prevent chip failures.
Source: Electronics Systems and Software, February 2004 | | | Set a course for free cores
L Collins (February 2004)
The open-source movement has come to hardware design with companies and alone designers providing cores for custom chips free of charge. But is it a viable way of cutting project costs?
Source: Electronics Systems and Software, February 2004 | | | Cost trade-offs in mixed-signal SoC designs
R Landry (February 2004)
Smart sensors and other single-chip industrial and medical devices can provide significant cost advantages over designs built from discrete parts, but care needs to be taken when selecting the implementation process to ensure you get the right cost and performance balance.
Source: Electronics Systems and Software, February 2004 | | | DSM interconnect effects on system-on-chip design flows
P Pezzati, Cadence Design Systems (February 2003)
Advanced deep submicron (DSM) processes can produce feature sizes of 0.10 microns and below, clock speeds of up to 2GHz, more than six layers of metal and many million gates on each chip. The combination of massive designs and physical effects due to new technologies is forcing designers to adopt new design methodologies.
Source: Electronics Systems and Software, February 2003 | | | Parallel processing beckons for cheaper basestations
C Edwards (February 2003)
Designing a 161 million transistor system-on-chip is one thing, but that is only part of the story if you want to change the way 3G basestations are designed.
Source: Electronics Systems and Software, February 2003 | Co-design frameworks Sorry, there are no articles for this topic.
System modelling | | Use-cases to aid safe design
M Hause, Artisan Software Tools (March 2004)
Safety is an important part of system design but it can be difficult to model. Use-cases provide a way of building the necessary information for an effective safety case.
Source: Electronics Systems and Software, April 2004 | | | Modelling to improve design-based yield
R Radojcic, PDF Solutions (March 2004)
The nature of defects in modern semiconductor processes mean that design features now have a controlling influence on yield. Working out which features work and which do not calls for the introduction of modelling techniques.
Source: Electronics Systems and Software, April 2004 | | | Transactions raise the bar for faster verification
B Vanthournout (February 2004)
Transaction-level modelling provides a way of trading off performance against timing accuracy to improve simulation speed, particularly for designs that rely on the combination of existing cores and new hardware.
Source: Electronics Systems and Software, February 2004 | | | FLO/STRESS: an integrated software module to predict stress in electronic products
C Bailey, M Warner, A Agha and K Pericleous, University of Greenwich and J Parry, C Marooney, H Reeves and I Clark, Flomerics Ltd (May 2002)
Software technology that predicts stress in electronic systems and packages, developed as part of TCS Programme, is described. The software is closely integrated within a thermal design tool providing the ability to simulate the coupled effects of airflow, temperature and stress on product performance. This integrated approach to analysis will help decrease the number of design cycles.
Source: Computing & Control Engineering Journal June 2002 | | | Fault simulation and modeling of microelectromechanical systems
R Rosing, A Lechner, A Richardson and A Dorey, Lancaster University (September 2000)
High-reliability and safety-critical markets for MEMS are driving new proposals for the integration of efficient built-in test and monitoring functions. The realisation of this technology will require support tools and validation methodologies, including fault simulation and testability analysis and full closed-loop simulation techniques to ensure cost and quality targets.
Source: Computing & Control Engineering Journal October 2000 |
Systems and Synthetic Biology | | Synthetic biologists tackel awareness issues
Chris Edwards (May 2008)
Researchers developing custom-built living organisms are recognising that they have to win public support for their work, writes Chris Edwards.
Source: Engineering & Technology - May 10th 2008 | | | Biological implementation of algorithms and unconventional computing
The Mexican iGEM team (November 2007)
The Mexican iGEM team is a recently established group whose main interest is the implementation of algorithms in biological systems. Their goal is to take advantage of the intrinsic features of these systems in order to explore new approaches to certain computations (unconventional computing). In the near future they plan to develop real-world applications that not only contribute to the understanding of specific problems in biology, computer science and related disciplines, but that also have a positive social impact.
Source: IET Synth. Biol., 2007, 1, (1–2), pp. 59–60 | Synthetic Biology | | Synthetic biologists tackel awareness issues
Chris Edwards (May 2008)
Researchers developing custom-built living organisms are recognising that they have to win public support for their work, writes Chris Edwards.
Source: Engineering & Technology - May 10th 2008 | | | Development of a novel biosensor for the detection of arsenic in drinking water
J Aleksic, F Bizzari, Y Cai, B Davidson, K de Mora, S Ivakhno, S L Seshasayee, J Nicholson, J Wilson, A Elfick, C French, L Kozma-Bognar, H Ma and A Millar (November 2007)
The University of Edinburgh iGEM2006 team sought to develop a whole-cell biosensor for the detection of arsenic in drinking water, a major problem in Bangladesh and West Bengal. The pH-reducing b-galactosidase part of the system was constructed and tested, and was found to give a clear response to arsenate concentrations as low as 5 ppb arsenic, well below the WHO recommended limit of 10 ppb.
Source: IET Synth. Biol., 2007, 1, (1–2), pp. 87–90 | | | Computing with living hardware
K A Haynes, M L Broderick, A D Brown, T L Butner, L Harden, L Heard, E Jessen, K Malloy, B Ogden, S Rosemond, S Simpson, E Zwack, A Malcolm Campbell, T Eckdahl, L J Heyer, and J L Poet (November 2007)
Our multi-institutional team of eleven undergraduates, one high school student, one postdoctoral fellow, and four faculty members explored the emerging field of synthetic biology and presented our results at the 2006 international Genetically Engineered Machine (iGEM) competition. Having had little or no previous research experience, biology, chemistry and mathematics students from four different institutions collaborated during the summer and fall semester of 2006. We identified the burnt pancake problem (sorting by reversals) as a mathematical puzzle ideal for solving with ‘living computer hardware’: Escherichia coli cells programmed to sort tandem fragments of DNA by reversals (DNA inversions or ‘flipping’).
Source: | | | New tools for self-organised pattern formation
K Bernhardt, E J Carter, N S Chand, J Lee, Y Xu, X Zhu, JW Ajioka, J M Goncalves, J Haseloff, G Micklem, and D Rowe (November 2007)
Position-dependent gene expression is a critical aspect of the development and behaviour of multicellular organisms. It requires a complex series of interactions to occur between different cell types in addition to intracellular signalling cascades. We used Escherichia coli to study the properties of an artificial signalling system at the interface between two expanding cell populations. We genetically engineered one population to produce a diffusible acyl-homoserine lactone (AHL) signal, and another population to respond to it. Our experiments demonstrate how such a signal can be used to reproducibly generate simple visible patterns with high accuracy in swimming agar...
Source: IET Synth. Biol., Vol. 1, No. 1–2, 2007 | | | Design of a biological half adder
M Terzer, M Jovanovic, A Choutko, O Nikolayeva, A Korn, D Brockhoff, F Zürcher, M Friedmann, R. Schütz, E Zitzler, J Stelling and S Panke (November 2007)
This paper presents the design of two logic gates, a biological AND and a biological XOR. They can be combined to produce a half-adder, one of the fundamental elements of complex systems engineering and represent a promising basis for the design of more complex genetic circuits.
Source: IET Synth. Biol., Vol. 1, No. 1–2, 2007 | | | The iGEM competition: building with biology
J. Brown (October 2007)
Can simple biological systems be built from standard, interchangeable parts and operated in living cells? Or is biology simply too complicated to be engineered in this way? The iGEM competition is an open design challenge for student teams that addresses this difficult question.
Source: iGEM 2007 | Systems Biology | | Synthetic biologists tackel awareness issues
Chris Edwards (May 2008)
Researchers developing custom-built living organisms are recognising that they have to win public support for their work, writes Chris Edwards.
Source: Engineering & Technology - May 10th 2008 | | | Statistical modelling of biochemical pathways
R.B. Burrows, G.R. Warnes and R.C. Hanumara (November 2007)
The usefulness of Bayesian statistical methods for the modelling of biochemical reactions is examined. With simulated data, it is shown that these methods can effectively fit mechanistic models of sequences of enzymatic reactions to experimental data. These methods have the advantages of being relatively easy to use and producing probability distributions for the model parameters rather than point estimates, allowing more informative inferences to be drawn.
Source: see IET Syst. Biol., 2007, 1, (6), pp. 353–360 |
Testing and verification | | Visionary Placement
Paul Rooimans, MYDATA (October 2004)
The growing trend for miniaturisation has challenged the abilities of electronics manufacturers to accurately place sensitive, high-performance components without damage. Somewhat surprisingly it is conventional vision systems technology that has emerged as the answer to these anxieties.
Source: Manufacturing Engineer - October 2004 | | | Working with assertions (programming)
Mark Peryer, Mentor Graphics (August 2004)
Assertions provide the ability to trap many problems in designs produced using hardware description languages and an assertion-based verification strategy allows designers to build reusable testbench code for faster design debugging.
Source: Electronics Systems and Software, August 2004 | | | Increasing the resolution of an analogue-to-digital converter
Agustin Schuster, Silicon Laboratories (August 2004)
Oversampling and averaging can be used to increase the resolution and signal-to-noise ratio of an on-chip ADC, as long as certain conditions are met - the main consideration being the issue of noise in the system and its source.
Source: Electronics Systems and Software, August 2004 | | | A path out of the verification wilderness
M Peryer & B Bailey, Mentor Graphics (March 2004)
Verification conitnues to eat up a huge amount of design project time with engineers being forced to re-implement testbenches at each stage. Assertions can help build reusable testbenches and cut down the time it takes to wipe out bugs in a forest of hardware description code.
Source: Electronics Systems and Software, April 2004 | | | Hardware-assisted design verification techniques
G Scholl, ProDesign GmbH (March 2004)
There may be as many functional ASIC verification methodologies as design projects started, given the many different design requirements, legacy situations, internal company rules, tools used, team members' experiences, to mention a few. It is therefore almost impossible to find a classification that encompasses them all, but this paper attempts to sort out some basic criteria.
Source: Electronics Systems and Software, April 2004 - online | | | Keep on running
C Evans-Pughe (March 2004)
As embedded systems become more complex, benchmark standards must evolve to stay relevant.
Source: IEE Review, March 2004 | | | Stalemate!
S Josifovska (March 2003)
Report from DATE 03 conference. The challenge of verification is becoming an obstacle to the use of IP blocks in semiconductor design.
Source: IEE Review April 2003 |
Training | | Measuring and diagnostic systems in biomedical education
K Jellonek and M Kotulska, Wroclaw University of Technology (January 2002)
A rising demand for specialists in measuring and diagnostic systems (MDS) able to apply multidisciplinary knowledge from medicine, theory of measurements, automation and physics was the stimulus for launching a course in this field for students of biomedical engineering at Wroclaw University of Technology. The course was to provide training in medical system design, development and implementation, and cover the topics of general mathematical models of the phenomena, data acquisition, data processing, interpretation and result visualisation. The main aim was to link modern technology with the traditional measurement approach to biological quantities. During the course students are presented with real-world problems from the field of medicine. This article outlines the course curriculum and its Web-centric approach to laboratory equipment.
Source: Engineering Science and Education Journal February 2002 |
| | Networks for this sector: Virtual communities on key areas of interest. | | |
